This invention relates to self-testing facilities for processor systems and the like and more particularly to a more efficient arrangement for self-testing of off-chip driver circuits having improved serviceability, reliability and that is easier to manufacture.
Testing systems of a useful nature have been described heretofore wherein processor elements have been checked, for example, for proper operation of registers and circuit chips.
The following patents are representative of the prior art.
U.S. Pat. No. 3,523,279 discloses a technique for checking register contents to verify the operability of both the registers and the bus which connects them.
U.S. Pat. No. 3,633,016 describes a testing technique which employs an I/O compare in conjunction with the application of a test signal.
U.S. Pat. No. 4,176,258 discloses the use of on-chip check circuits for testing purposes.
U.S. Pat. No. 4,159,534 describes a register and bus checking scheme in which a comparison is made between the contents of the input and output registers.
U.S. Pat. Nos. 4,236,246; 4,266,293; 4,163,210 and 4,178,582 all disclose other testing techniques of incidental interest.
The primary objective of the present invention is to accomplish self-testing of circuit chips and a system bus structure.